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[Crack Hack] des

Description: 用VERILOG语言实现的数据加密标准代码,在QUARTUS5.1上仿真过
Platform: | Size: 1437030 | Author: zhang feng | Hits:

[Other Embeded program] DES verilog代码

Description:
Platform: | Size: 9483 | Author: twywgj@163.comtwywgj | Hits:

[Communication] DES

Description: verilog编写的DES安全芯片代码
Platform: | Size: 18907 | Author: jinhfut@163.com | Hits:

[Crack Hack] 3fast_des

Description: 一个快速实现3des的算法，分别用vhcl和Veriloge语言进行编写，很实用-a rapidly 3des algorithm respectively vhcl Veriloge language and prepared very practical
Platform: | Size: 31744 | Author: 王明 | Hits:

[Crack Hack] DES_Verilog

Description: 这是我用Verilog写的DES加解密程序,准确的说这是一份实验报告,里面不但有程序还有简单的注释[主要是针对仿真的波形的],我主要写的是主控部分,密钥生成部分参考了下版原康宏的程序.该程序即可加密也可解密,选用CycloneII器件即能跑到100Mhz以上.-This is what I used to write Verilog the DES encryption and decryption procedures, accurate to say that this is a test report, which not only have a simple Notes program [is mainly directed against the waveform simulation], I write is the main control part key generation is partly based on the next version of the original Yasuhiro procedures. The program can also be encrypted can be decrypted, CycloneII optional devices which can run more than 100Mhz.
Platform: | Size: 296960 | Author: jesse | Hits:

[VHDL-FPGA-Verilog] DES

Description: DES加密算法的VHDL实现,采用流水线技术实现-The VHDL implement of DES encrypt algorithmic
Platform: | Size: 17718272 | Author: Mr Yang | Hits:

[Crack Hack] tripledes

Description: 3-DES加密IP核VHDL源码，3次DES流水执行-VHDL source code for 3-DES encryption IP core, pipelined execution
Platform: | Size: 31744 | Author: Yan, Like | Hits:

[VHDL-FPGA-Verilog] des_Vhdl

Description: VHDL & Verilog Synthesizable model of the Data Encryption Standard (DES)
Platform: | Size: 47104 | Author: changjc | Hits:

[Crack Hack] aes_thesis_v1.0

Description: AES VERILOG CODE 128 192 32DES比較-AES VERILOG CODE 128 192 32DES Comparison
Platform: | Size: 386048 | Author: 蕭嵎之 | Hits:

[Crack Hack] DES_Encrypt_Decrypt_Verilog

Description: DES加密算法的Verilog HDL实现，带模式选择端口，可以实现加密和解密，已经modelsim仿真通过。-Des En/Decrypt,Verilog HDL code
Platform: | Size: 8192 | Author: Amazing_Eric | Hits:

[VHDL-FPGA-Verilog] mos_des

Description: DES算法的verilog实现，可以研究下。-DES for Verilog。
Platform: | Size: 33792 | Author: lina | Hits:

[Crack Hack] topic

Description: DES加密算法的VHDL和VERILOG源程序- Xilinx开源共享61EDA代码工厂-DES encryption algorithm of VHDL and VERILOG source code- Xilinx factory open source code sharing 61EDA
Platform: | Size: 274432 | Author: renkaiqiang | Hits:

[VHDL-FPGA-Verilog] LIP1601CORE_des_3des

Description: DES & 3DES VHDL & Verilog code
Platform: | Size: 7723008 | Author: jc | Hits:

[VHDL-FPGA-Verilog] LIP1602CORE_des

Description: Verilog DES Encrption Module
Platform: | Size: 36864 | Author: jc | Hits:

[VHDL-FPGA-Verilog] des1

Description: 对称密码算法des的Verilog语言实现，已经测试通过。欢迎下载！-Symmetric cryptographic algorithm of des Verilog language implementation, has the test pass. Welcome to download!
Platform: | Size: 15360 | Author: 杨俊明 | Hits:

[VHDL-FPGA-Verilog] des

Description: des的Verilog代码（已编译，可直接使用）-des Verilog code (compiled, and can be used directly)
Platform: | Size: 2048 | Author: shilei | Hits:

[VHDL-FPGA-Verilog] DES

Description: 该源码采用DES加密标准，采用Verilog编写，时钟为50M，可以扩展为硬件级加密系统-The source uses DES encryption standard, Verilog prepared, the clock is 50M, can be extended to hardware-level encryption system
Platform: | Size: 16216064 | Author: Eason | Hits:

[VHDL-FPGA-Verilog] DES算法的verilog实现

Description: 用verilog实现的DES算法。模块划分详细。可以用modelsim验证。
Platform: | Size: 103060 | Author: cjc87267137 | Hits:

[VHDL-FPGA-Verilog] DES-Verilog-master

Description: DES加密算法硬件verilog实现，包含testbench，加密主模块encrypt，明文变换模块LRToCiphertextConverter，NextRi模块等子模块。-DES encrypt verilog
Platform: | Size: 11264 | Author: lv | Hits:

[Crack Hack] 21ic下载_快速DES算法

Description: des代码,using verilog HDL,方便I使用(des code, using by verilog HDL.)
Platform: | Size: 5120 | Author: binbinlee | Hits:
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